Catalogue


11th Asian Test Symposium (ATS'02) [electronic resource] : proceedings of the 11th Asian Test Symposium : 18-20 November, 2002, Guam, USA /
sponsored by the IEEE Computer Society Test Technology Technical Council (TTTC) ; in cooperation with Technical Group on Dependable Computing, IEICE, Special Interest Group on System LSI Design Methodology, IPS Japan.
imprint
Los Alamitos, California : IEEE Computer Society, c2002.
description
xxi, 437 p. : ill. ; 28 cm.
ISBN
0769518257
format(s)
Book
A Look Inside
Reviews
This item was reviewed in:
SciTech Book News, March 2003
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Table of Contents
General Chair's Messagep. xi
Program Chair's Messagep. xii
ATS'01 Best Paper Awardp. xiii
ATS Steering Committeep. xiv
Organizing Committeep. xv
Program Committee and Voluntary Reviewersp. xvi
TTTC Activities Boardp. xix
Test Generation
On Generating High Quality Tests for Transition Faultsp. 1
Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Testsp. 9
Maximum Distance Testingp. 15
On-Line Testing
High Precision Result Evaluation of VLSIp. 21
A Totally Self-Checking Dynamic Asynchronous Datapathp. 27
Non-intrusive Design of Concurrently Self-Testable FSMsp. 33
Analog and Mixed Signal Testing
Test Limitations of Parametric Faults in Analog Circuitsp. 39
Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devicesp. 45
On-Chip Analog Response Extraction with 1-Bit [Sigma]-[delta] Modulatorsp. 49
Test Set Compaction
A State Reduction Method for Non-scan Based FSM Testing with Don't Care Inputs Identification Techniquep. 55
Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequencesp. 61
Test Data Compression Using Don't-Care Identification and Statistical Encodingp. 67
Design for Testability
Design for Two-Pattern Testability of Controller-Data Path Circuitsp. 73
MD-SCAN Method for Low Power Scan Testingp. 80
Non-scan Design for Testability Based on Fault Oriented Conflict Analysisp. 86
Memory Testing 1
Specification and Design of a New Memory Fault Simulatorp. 92
DRAM Specific Approximation of the Faulty Behavior of Cell Defectsp. 98
An Access Timing Measurement Unit of Embedded Memoryp. 104
Delay Fault Testing
A Partitioning and Storage Based Built-in Test Pattern Generation Method for Delay Faults in Scan Circuitsp. 110
Optimal Seed Generation for Delay Fault Detection BISTp. 116
On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communicationsp. 122
Test Synthesis
A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Designp. 128
Test Requirement Analysis for Low Cost Hierarchical Test Path Constructionp. 134
Testable Realizations for ESOP Expressions of Logic Functionsp. 140
Memory Testing 2
DPSC SRAM Transparent Test Algorithmp. 145
Tests for Word-Oriented Content Addressable Memoriesp. 151
A High Performance I[subscript DDQ] Testable Cache for Scaled CMOS Technologiesp. 157
Crosstalk Fault Testing
Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topologyp. 163
A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signalp. 170
Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuitsp. 176
A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuitsp. 182
Built-in Self Test 1
Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automatap. 188
Fault Set Partition for Efficient Width Compressionp. 194
A Reseeding Technique for LFSR-Based BIST Applicationsp. 200
A ROMless LFSR Reseeding Scheme for Scan-Based BISTp. 206
Fault-Tolerance
A Fault-Tolerant Architecture for Symmetric Block Ciphersp. 212
A New Learning Approach to Design Fault Tolerant ANNs: Finally a Zero HW-SW Overheadp. 218
Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systemsp. 224
Easily Testable and Fault-Tolerant Design of FFT Butterfly Networksp. 230
Fault Detection and Diagnosis
Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGA'sp. 236
Reduction of Target Fault List for Crosstalk-Induced Delay Faults by Using Layout Constraintsp. 242
Diagnosis of Byzantine Open-Segment Faultsp. 248
Built-in Self Test 2
Robust Space Compaction of Test Responsesp. 254
An Evolutionary Strategy to Design an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS)p. 260
An Embedded Built-in-Self-Test Approach for Analog-to-Digital Convertersp. 266
Software Testing
Statistical Analysis of Time Series Data on the Number of Faults Detected by Software Testingp. 272
An Analytic Software Testability Modelp. 278
Effective Automated Testing: A Solution of Graphical Object Verificationp. 284
Special Session--Test Strategies and Case Studies for SoC in Industries
At-Speed Built-in Test for Logic Circuits with Multiple Clocksp. 292
A Test Point Insertion Method to Reduce the Number of Test Patternsp. 298
A SoC Test Strategy Based on a Non-scan DFT Methodp. 305
Embedded Test Solution as a Breakthrough in Reducing Cost of Test for System on Chipsp. 311
Manufacturing Test of SoCsp. 317
Recent Advances in Test Planning for Modular Testing of Core-Based SoCsp. 320
Test Power Reduction
A Method to Reduce Power Dissipation during Test for Sequential Circuitsp. 326
Test Power Optimization Techniques for CMOS Circuitsp. 332
Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disablingp. 338
System-on-Chip Testing 1
A Simple Wrapped Core Linking Module for SoC Test Accessp. 344
Testing System-on-Chip by Summations of Cores' Test Output Voltagesp. 350
Test Scheduling of BISTed Memory Cores for SoCp. 356
Verification and Simulation
Effective Error Diagnosis for RTL Designs in HDLsp. 362
Evolutionary Test Program Induction for Microprocessor Design Verificationp. 368
Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Modelsp. 374
Test Systems
Testing Embedded Systems by Using a C[superscript ++] Script Interpreterp. 380
Extending EDA Environment from Design to Testp. 386
Vector Memory Expansion System for T33xx Logic Testerp. 392
System-on-Chip Testing 2
Integrated Test Scheduling, Test Parallelization and TAM Designp. 397
Core - Clustering Based SoC Test Scheduling Optimizationp. 405
Test Scheduling and Test Access Architecture Optimization for System-on-Chipp. 411
Current Testing
CMOS Floating Gate Defect Detection Using I[subscript DDQ] Test with DC Power Supply Superposed by AC Componentp. 417
Test Time Reduction for I[subscript DDQ] Testing by Arranging Test Vectorsp. 423
Time Slot Specification Based Approach to Analog Fault Diagnosis Using Built-in Current Sensors and Test Point Insertionp. 429
Author Indexp. 435
Call for Papers of ATS'03p. 437
Table of Contents provided by Syndetics. All Rights Reserved.

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